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NanoSpice Giga

Large Capacity & High Precision SPICE

Introduction

NanoSpice Giga is industry's Giga-scale SPICE simulator, its innovative parallel simulation engine is built using big data architecture that effectively handles billion-element designs. This capability makes NanoSpice Giga ideally suited for verification and signoff of memory, custom or semi-custom digital circuits, and fullchip designs.  

NanoSpice Giga is designed for accuracy verification and signoff of advanced memory designs, an area where traditional FastSPICE has fundamental limitations. Pure SPICE engine of NanoSpice Giga offers significantly higher accuracy for power, leakage, timing/ noise characterizations and verification. NanoSpice Giga's superior parallelization technologies deliver faster simulation speed without sacrificing accuracy. With high accuracy and performance, NanoSpice Giga can serve as the golden signoff simulator for memory IP and full chip verification.  



Key Advantage

 Superior accuracy :Pure SPICE accuracy with DC convergence 

Giga-scale capacity :Ability to handle full chip verification and signoff (>109 elements) 

High performance :Scalable to 32+ threads, high performance parallelization. Special optimization for FinFET/FD-SOI processes 

No need for complicated options:No tuning, directly replaces existing simulator 

Foundry validated accuracy :16/14/10/7/5nm FinFET and 28nm FD-SOI ready  

Applications

Memory IC high accuracy verification (Flash, DRAM, SRAM, MRAM etc.) 

Panel (LCD/OLED) circuit high accuracy simulation and verification 

Large scale analog circuit post simulation and verification 

Full chip SoC high accuracy simulation and verification  

Specifications

Supports Hspice and Spectre netlist formats

Supports all public domain models, user-defined models 

-- MOSFET: BSIM3, BSIM4, BSIM-BULK, BSIM-IMG, BSIM-CMG, BSIM-SOI, LETI-UTSOI, PSP, HiSIM2, HiSIM_HV, EKV3 

-- BJT: MAXTRAM, VBIC, HICUM; TFT: a-Si TFT, poly-Si TFT 

-- Diode: JUNCAP, JUNCAP200, DIODE_CMC; Varactor: MOSVAR 

-- Resistor: R2_CMC, R3_CMC; HEMT: ASM-HEMT; JFET/MESFET; TMI/Custom PMI; Bsource Supports full SPICE analysis features 

-- OP, DC, AC, Noise, Transient, Trannoise, FFT, Sweep, Alter, Bisection Stability, Pole-Zero, MonteCarlo, DC Match, AC Match Supports Verilog-A (LRM2.4) and behavioral sources 

Supports VEC and VCD stimulus files 

Supports standard output formats for data analysis: FSDB, PSFASCII, SPICEASCII, ASCII, etc 

Supports S-parameter, Transmission line (W element, T element), IBIS model 

Supports SPEF, DSPF, DPF back-annotation 

Supports Verilog co-simulation 

Drop-in replacement of any FastSPICE simulator in existing design flows    


  Applications Example

Idd verification of SRAM full chip including 4.95E8 devices by NanoSpice Giga using default option settings