NanoSpice Pro is a high-performance, high-capacity revolutionary FastSPICE circuit simulator. It boosts productivity of modern complex designs including memory (DRAM, SRAM, Flash, MRAM), FPGA, custom digital and SoC.
With its breakthrough FastSPICE algorithm, intelligent topology recognition and automatic partition technology, NanoSpice Pro delivers superior performance and capacity to address advanced nodes verification challenges.
The adaptive dual-solver ensures the analog accuracy and digital performance for mixed-signal design excellence, benefiting from a seamless integration of the state-of-the-art digital engine and the giga-scale analog engine.
NanoSpice Pro provides a one-stop memory simulation solution to meet all needs from memory cell design, memory array and compiler verification, memory characterization, and full-chip verification with up to 10X+ performance increase over other commercial simulators.
Breakthrough FastSPICE algorithm, intelligent topology recognition and automatic partition
Higher capacity, up to 10X+ faster simulation throughput
Advanced RC reduction and fast yet accurate model evaluation
Adaptive dual-solver, analog accuracy and digital performance
Performance scales linearly with 32+ multi-core simulations
One-stop memory simulation solution
|| NanoSpice Pro
|| Other Simulator
|3.9 days||25.2 days||6.5X|
|4.2 hours||35.5 hours||8.5X|
|1.6 days||6.6 days||4.1X|
Hspice and Spectre netlist formats
Standard models: BSIM3, BSIM4, BSIM-BULK, BSIMSOI, BSIM-CMG, UTSOI, PSP, HiSIM2, HiSIM_HV, GP-BJT, VBIC, HICUM, Mextram, JFET, MESFET, RPITFT, etc.
TMI, Verlog-A and behavior sources
IBIS model ,S-parameter and transmission line
Standard outputs: FSDB, PSFASCII, ASCII, SPICEASCII, etc.
Transient output format - nwf, reduce 2x+ file size
VEC and VCD stimulus files
DSPF and SPEF back-annotation
Drop-in replacement of FastSPICE in existing flows
Supports Verilog co-simulation
Support pubilc/hybrid cloud, computer farm
Memory IC designs (DRAM, SRAM, Flash, Memory IP characterization and chip verification)
FPGA, SoC chip fast timing and functional verification
Custom or semi-custom digital: clock tree, critical path analysis