Introduction
NanoSpice™ is a new generation high-capacity, high-performance parallel SPICE simulator, designed for challenging simulation jobs, such as large post-layout analog circuit simulations requiring capacity, speed and accuracy measurements simultaneously. NanoSpice’s superior parallelization technologies handle generic circuit simulation with up to 50M+ circuit elements. This invaluable advantage to NanoSpice, enables it to deliver better performance than contrasting parallel SPICE simulators in large simulation jobs. NanoSpice also has an innovative, efficient and cost-effective parallelization license model.
Key Benefits
Accuracy: Pure SPICE engine matching industry's accuracy standard
5X+ larger capacity: 50M+ element circuit capacity for generic circuit types
Fastest parallel SPICE: faster than other parallel SPICE simulators
Drop-in replacement: standard input/output formats and compatible SPICE analysis features
Foundry validated accuracy: 14/7/5nm FinFET and 28nm FD-SOI ready
Applications
Analog (ADC, PLL, PMIC) and I/O (SerDes)
Memory characterization and verification (DRAM, SRAM, flash, etc)
Custom digital, standard cell
Library characterization
Design Flow Integration
Drop-in replacement of any SPICE simulator in existing design flows for any transistor-level circuit simulations
Plug and run without any special options
Specifications
Supports Hspice and Spectre netlist formats
Supports standard output formats for data analysis: FSDB, PSFASCII, SPICEASCII, ASCII, etc
Unique transient output format - nwf, reduce 2x+ file size
SPICE analysis features: OP, DC, AC, Noise, Tran, Info, Sweep, Alter, Stability, FFT, Bisection, Pole-Zero, DC Match, AC Match, Monte Carlo, PVT, Tran Noise, etc
Supports all public domain models, user-defined models
MOSFET models include BSIM3, BSIM4, BSIM6, BSIMSOI, BSIM-CMG, BSIM-IMG, UTSOI, PSP, HSIM2 , HiSIM_HV, MOS9, MOS11
Bipolar models include Gummel-Poon, VBIC, HICUM, Mextram
Diode, JFET, MESFET, RLC, TFT, TSMC model interface (TMI)
Supports Verilog-A and behavioral sources
Supports VEC and VCD stimulus files
Supports SPEF, DSPF, DPF back-annotation
Supports IBIS model, S-parameter and transmission line, etc
Platform Supported:
64bit Redhat Enterprise V5.x, V6.x, V7.x, V8.x ;
64bit CentOS V5.x, V6.x, V7.x, V8.x
Multi-core server or computer farm
Cloud