Hierarchical SoC Design Planning Solution



NavisPro is the power and the timing aware RTL design planning solution which predicts and prevents the physical implementation problems. It provides SoC design planning solution to find the optimal number of power pads and their locations to meet the target IR-drop and Simultaneous Switching Noise (SSN) margin in the early design stage. NavisPro enables designers to minimize the unnecessary design iterations and to achieve the time to market of the SoC designs.Hierarchical floorplanning unique solutions to resolve the complexity problem of SoC designs. It also provides hierarchical floorplanning the full chip design is partitioned into many sub-systems. Each sub-subsystems layout is implemented independently. In this design environment, the chip partitioning includes the physical hierarchical partitions of the design and the pin placements of each sub-systems. The pin placement of sub-system is one of the critical constraints of sub-system layout and it determines the quality of the full-chip level routing congestion. In modern SoC designs, many processors are used in a single chip. The accurate estimation of the bus interconnect timings between sub-systems are critical for the timing closure. The estimation of the interface net timing across the design hierarchy is very useful feature for the full chip level interface net timing. 

Key Advantage


  • Constraint driven RTL floorplanning
  • Feasibility analysis of package design
  • Fast design iteration


  • Visualized RTL design exploration & debugging
  • Visualization of the clock tree structure and clock design rule check
  • Validation and edition of power constraints with graphical debugging environment
  • Design constraints management in early design stage


Floorplanning & feasibility analysis of SoC design in RTL design stage

IO pad configuration with bump pads structuring for flip-chip style design

RTL & gate-level cell-based digital (logic) design 



  • Hierarchical Floorplanning

  • Constraint driven RTL floorplanning

-- Efficient pin assignment

-- Bus interconnect analysis

-- Interconnect net delay estimation

-- Routing congestion analysis

-- Bump array generation

  • With PadOptima optional

-- Optimal pad configuration

-- RDL routing feasibility analysis


  • RTL design exploration with multi-level schematic

  • Area estimation

  • Clock structure analysis

  • Low power design intent analysis
  • Analytic power estimation

 Application Example   

Constraint Driven Floorplanning

Automatic / Manual Pin Assignment

Routing Congestion Estimation


Bus Interconnect Planning


Hierarchical Floorplanning