Advanced PDK Verification Platform


PQLab is an advanced PDK(Process Design Kit) verification platform.As semiconductor manufacturing technology continuously scales down, the complexity and scale of the PDK is increasing rapidly, so that the PDK validation is much more difficult than ever before and takes longer and longer. To resolve this problem, Primarius developed PQLab as a complete solution based on years of experiences in advanced PDK development and verification. 

PQLab is an automated QA software for PDK, which is equipped with kinds of qualification mechanisms of PDK integrity, Tech files, PCell CDF, PCell physical verification (DRC & LVS), and SPICE models. It could handle PDK verification from 0.35um to 22nm of the planar process and also from 16nm to 5nm FinFET process, cover the application in digital logic, analog, high voltage and RF circuit. Help foundries PDK engineers to ensure PDK quality, and help IC designers to easily analyze and qualify foundry PDKs, benchmark between different versions and different design flows.  

Key Advantage

Versatility:Support mainstream foundries PDK format and EDA tools

Completeness:Support PCell, DRC/LVS, simulation and Tech file fully validation Support performance benchmark between different PDK versions and various combination of different models, LVS, and PEX 

Automation:Highly - integrated automation PDK QA 

Efficiency:Built-in pattern generation module for each PDK component 

Flexibility:Support test pattern user customization 

Reusability:Existing PDK QA setting could be reused in future project  


Test pattern generation automation 

Automatically generates the test patterns for DRC, LVS, CDF or other PDK components 

Support CDF Verification 

CDF Spec, CDF Callbacks ,CDF Parameter and SPICE Model parameterconsistency inspection 

Support DRC/LVS Verification 

Intelligently auto-generates the minimal set of the DRC and LVS inspection test pattern to ensure the PDK could work under any PCell parameter combination 

Support comprehensive simulation 

Ensure the PDK output rationality through automatic comparison between pre-layout and postlayout simulation

Support to compare the results from different combinations of SPICE model, LVS and PEX 

Support DC OP back-annotation function verification Support Pcell input variable function verification  


Foundries process development 

Foundry PDK development and verification 

Fabless & IP vendor evaluate and verify foundries process  

 Application Example