As the complexity of SoC design is increasing according to high-performance requirements, the number of components is growing exponentially in SoC design. So, I/O pad configuration planning and chip-to-package connectivity verification with package design are required earlier than traditional design methodology. This is becoming a crucial issue for time-to-market in the SoC industry.
In addition, the automated and standardized task of verifying the system connectivity from I/O pads to ball on the package has not been done, so it causes many errors & defects. Accordingly, it is necessary to establish seamless and robust chip-to-package connectivity verification methodology, as well.
sPadInspector is the unique and robust chip-to-package connectivity verification solution. It enables to verify integrated system connection with extraction of the connectivity between chip and package design.
Recently, system packaging has been manufactured in various types. Accordingly, sPadInspector supports the following types of packaging styles to meet this diversity.
- SiP (System in Package) & MCP (Multiple chip package)
- 2.5D – RDL interposer
- PoP (Package on package)
- Achieve error-free chip-to-package connectivity
- Early design engagement for package design
- Reduce long design iteration
- Support various package type
- Efficient communication method
- Package designing interface
- Back-end designing with RDL
- IO pad cell & circuit designing
- I/O specification validation check
- Extraction & integration of the connectivity between chip & package
- Diagraming of system connectivity between chip & package
- Consistency check of heterogenous design data
- Chip-to-package connectivity verification
Pad to bump connectivity extraction & Design consistency check
Chip & package design integration
Chip-to-package connectivity verification
Chip & package connectivity diagram