PRIMARIUS - Digital Design EDA

Large-Scale IC Design & Verification

Supporting SoC chip planning and verification, timing verification and standard cell library characterization and verification to predict and prevent design problems in advance, while enabling customers to efficiently create Standard Cell Library.

Standard Cell

The Standard Cell Library is a standardized circuit cell library that plays a vital role in integrated circuit design. It encompasses a range of logic gate circuits that enable the implementation of complex digital circuit designs. It's usually provided by foundries for IC designers to optimize chip PPA.

Primarius Standard Cell Library solution employs advanced distributed parallel architecture technology and cutting-edge cell circuit analysis and extraction algorithms. Empowered with our high-precision SPICE simulator, it is represented by the fast and high-precision standard cell library characterization platform NanoCell, providing a complete solution for automated design, library characterization, and verification of standard cell libraries.

Planning & Verification

RTL (Register Transfer Level) design is a commonly used design method in digital IC design. RTL design planning involves various aspects of the design, including the functionality, performance, power consumption, timing, and area. Through RTL design planning, designers can perform comprehensive analysis and optimization of the chip in the early stages of design, avoiding serious issues and delays during later design and verification processes.

Primarius design planning and verification solution not only supports early-stage RTL-level power and timing design planning to predict and prevent potential problems in later stages of design, but also supports connectivity validation between chip and package design at even earlier design stages, thereby improving chip design reliability, accelerating time to market, and reducing costs and risks.

Timing Verification

In SoC circuit design, critical paths are crucial for circuit performance and power consumption. By analyzing the critical path and performing timing verification, designers can help designers identify bottlenecks in the circuit, optimize circuit performance and power consumption, and improve circuit stability and reliability. Additionally, timing verification ensures that the circuit timing meets specifications preventing timing faults and reducing the cost and time of circuit verification and optimization.

Primarius timing verification tools support mixed gate-level and transistor-level timing analysis, as well as critical path analysis. Even without a standard cell library, customers can use transistor-level critical path analysis to complete complex SoC timing analysis. The tools are flexible to adapt to different design needs and scenarios, providing comprehensive features that help customers achieve their design goals efficiently.

Digital Design EDA

Standard Cell

Library Characterization

NanoCell

Library Validation

LibWiz

Planning & Verification

SoC Design Planning

NavisPro

Chip-to-Package Verification

PadInspector

Timing Verification

Timing Analysis

TRASTA

Path Analysis

PathInspector

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