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Gate-TR Mixed-Level Timing Analysis Solution

Mixed-Level Timing Analysis Custom Cell Characterization Built-in STA engine

TRASTA automatically identifies the critical path and enables designers to analyze the critical path with the highest precision. 

  • Identifies unique devices of the design and generates gate level circuit

  • Topology matching and channel connected extraction techniques

  • Timing characteristics of extracted gate-level cells are automatically characterized and used in Static Timing Analysis (STA) step

  • Built-in STA engine and SPICE netlist generation capability with back-annotated parasitics

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  • Efficiency

    Efficient critical path tracing at the full-chip level

  • Automation

    Automatic critical path extraction with parasitics

  • Customization

    On the fly custom cell characterization

  • Unity

    Unified environment for STA & dynamic simulation


  • Custom cell characterization

  • Timing analysis of
    mixed design

  • Re-characterization of standard cell

  • Timing analysis of CPU
    datapaths/Digital IPs

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