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Hierarchical SoC Design Planning Solution

RTL Design Planning Hierarchical Floorplanning Global Channel Planning

NavisPro provides an RTL SoC design planning solution that predicts and prevents the design issues commonly found in the physical implementation stage. 

  • Constraints-driven RTL design floorplanning for better QoR

  • Addresses complexity problem of SoC design via intelligent partitioning of the full chip into many blocks or sub-systems

  • Chip partitioning includes physical hierarchical partitions of the design and pin placement of each sub-system

  • Accurate estimation of the bus interconnect timing between sub-systems

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  • Mixed Levels

    Mixed-level design planning (RTL/Gate/Black-box)

  • Flexibility

    Flexible design abstraction management

  • Rich Features

    Rich sets of key engineering features

  • Automation

    Automatic block pin assignment &
    bus interconnect planning

  • Ease of Use

    Efficient RTL design planning with minimum efforts for input data preparation

  • Efficiency

    Reducing design TAT
    by minimization of design iterations


  • Large & complex
    SoC design

  • Design & constraints exploration

  • Constraints-driven floorplanning

  • Automatic/manual
    pin assignment

  • Routing congestion estimation

  • BUS interconnect planning

  • Hierarchical floorplanning

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